1. Field of the Invention
The invention relates to contact free integrated circuit cards, also called contact free smart cards, and more particularly the circuits in such cards that analyse binary signals received by the card to detect data frames and to update them in parallel form for their processing.
2. Description of Related Art
A contact free smart card comprises (FIG. 1):                an antenna 10 that detects radio frequency signals at the carrier frequency Fo sent by a transmitter from a remote reader and that transmits signals to the reader,        a radio frequency interface 12,        a logic block 14, and        a memory 16.        
On reception, the radio frequency interface 12 receives signals detected by the antenna 10 and outputs firstly a regulated voltage Vdd that supplies power to the different electronic circuits, and secondly data signals and clock signals that are applied to the logic block 14.
On reception, the logic block 14 analyses the serial binary signals to present them in parallel form in the registers so as to interpret them in the form of operations such as read, write or erase data to be carried out in the memory 16.
The address in the memory 16 is given by the contents of one or several of the registers mentioned above, and the same is applicable for the data to be written in the memory 16.
In response to a command, the logic block 14 may carry out a read data operation in the memory 16 and may carry out processing on this data.
The data read in the memory, possibly after being processed by the logic block 14, is transmitted to the radio frequency interface 12 that outputs modulation signals applied to antenna 10 for transmission to the remote reader.
The binary signals that are sent by the remote reader, and which therefore have to be analysed by the logic block 14, are in the form of frames of binary digits “1” or “0” with formats defined by standards.
Thus, FIG. 2-a is an example of a frame format according to standard ISO14443-3, whereas FIG. 2b is an example of a frame format according to standard ISO15693-3.
Thus, the frame according to standard ISO14443-3 begins (references 20 and SOF) by a start of frame with ten to eleven “0” followed by two “1” binary digits and terminates (references 22 and EOF) by an end of frame with ten to eleven “0” followed by a “1”.
For example, the start SOF is followed by a byte 24 indicating the read command, then n bytes (reference 26) corresponding to the address in memory 16, and two error check bytes (reference 28) more frequently known under the abbreviation CRC (Cyclic Redundancy Check).
Similarly, the frame according to ISO standard 15693-3 begins with a start of frame SOF 30, and finishes with an end of frame EOF, 32. For example, the start of frame SOF is followed by a Request byte 34, then a Command byte 36, then n data bytes 40 and two CRC bytes 38.
To detect a frame, the logic block 14 must analyse the sequence of binary signals output by the radio frequency interface to detect a start of frame SOF. When this start of frame is detected, the binary digits of the following bytes are detected as they arrive and are saved in registers, each register corresponding to one byte.
After an error check using two CRC bytes, the contents of the registers is validated which corresponds to validating the received frame. The planned operation (save, read or erase) may then be determined by decoding the contents of one of the registers, and then be executed.
This method of analysing binary signals to detect a frame and to present it in parallel form, and to validate it and decode it, leads to a relatively long frame processing time while the time available to carry out all the processing is limited by the time for a contact free smart card to pass in front of the reader.
Therefore, one purpose of this invention is to make a data frame detection circuit and to format the data frames for which the processing time is very short.